资讯

EDN18 年

Cadence and Mentor create free, open-source SystemVerilog methodology

In an effort to make it easier for IC designers to create interoperable SystemVerilog verification flows, Cadence Design Systems and Mentor Graphics today announced that they have jointly created—and ...
EDN22 年

Injunction may restrict Cadence use of simulation tech

SANTA CRUZ, Calif. — A preliminary injunction obtained by a small EDA vendor may block Cadence Design Systems Inc. from using the mixed-signal Verilog simulation technology obtained in the acquisition ...
Business Wire5 年

Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation With up to 5X Faster ...

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence ® Xcelium ™ Logic Simulator has been enhanced with machine learning technology (ML), called ...
Semiconductor Engineering6 年

Re-using Common Simulation Set-Up Processes To Speed Regression

Functional verification of SoCs always has some kind of set up process. For complex SoCs, at least, this initial set up phase often consumes from 20 to 90% of each test’s total simulation time. And ...